Virtually all wireless communication systems require local oscillators for up-conversion and down-conversion of their transmitted and received signals. Most commonly, the local oscillators are implemented as fractional-N PLLs (phase locked loops). Fractional-N PLLs can generate a high quality, high frequency signal from a digital input stream and a lower frequency reference waveform.
The spectral purity of the local oscillator in a transceiver is a critical factor in overall transceiver performance. Communication standards therefore explicitly or implicitly stipulate stringent phase noise requirements on the local oscillators. Most standards dictate the maximum acceptable phase noise power in various frequency bands. Additionally, most standards require that spurious tones in the local oscillator's phase noise be highly attenuated, particularly in critical frequency bands. DACs also have stringent spurious tone requirements in wireless applications, digital audio applications and instrumentation applications. Digital audio and instrumentation spurious tone requirements are particularly critical in many consumer products.
Modern digital-to-analog converters (DACs) and fractional-N phase-locked loops (PLLs) rely upon a digital delta-sigma modulator (ΔΣ modulator) to coarsely quantize a constant or slowly varying digital sequence. The quantized sequence can be viewed as the sum of the original sequence plus spectrally shaped quantization noise that has most of its power outside of a given low-frequency signal band. Ultimately, the quantized sequence is converted to an analog signal and further processed by analog circuitry including a low-pass filter to suppress quantization noise outside of the signal band.
FIG. 1 is a block diagram of a conventional ΔΣ fractional-N PLL. The purpose of the system is to generate an output signal of frequency (N+α)fref where N is a positive integer, a is a constant fractional value between 0 and 1, and fref is the frequency of a reference oscillator. The system consists of a phase-frequency detector (PFD) and a charge pump 100, a loop filter 102, a voltage controlled oscillator (VCO) 104, a multi-modulus divider 106, and a digital ΔΣ modulator 108. The divider output, vdlv(t), is a two-level signal in which the nth and (n+1)th rising edges are separated by N+y[n] periods of the VCO output, for n=1, 2, 3, . . . , where y[n] is a sequence of integers generated by the ΔΣ modulator 108. As indicated in FIG. 1B for the case where the PLL is locked, if the nth rising edge of the reference signal, vref(t), occurs before that of vdlv(t), the charge pump 100 generates a positive current pulse of magnitude lCP with a duration equal to the time difference between the two edges. This increases the VCO control voltage; vctrl(t), thereby increasing the VCO output frequency. Alternatively, if the nth rising edge of vref(t), occurs after that of vdlv,(t), the situation is similar except the polarity of the current pulse is negative, which decreases the VCO frequency. This causes the output frequency to settle to fref times the sum of N and the average of y[n].
If y[n] could be set directly to the desired fractional value, a, directly then the output frequency of the PLL would settle to (N+α)fref, thereby achieving the goal of the fractional-N PLL. Unfortunately, y[n] is restricted to integer values because the divider 106 is only able to count integer VCO cycles whereas a is a fractional value. To circumvent this problem y[n] is designed to be a sequence of integers that average to α. The input to the ΔΣ modulator 108 is α plus pseudo-random least significant bit (LSB) dither, so its output has the form y[n]=α+s[n], where s[n] is a zero-mean sequence consisting of spectrally shaped ΔΣ quantization noise and LSB dither. The dither prevents s[n] from containing spurious tones that would otherwise show up as spurious tones in the PLL's output. Hence, the output frequency settles to an average (N+α)fref, as desired, although s[n] introduces phase noise.
For most wireless applications spurious tones can be sufficiently suppressed only with design tradeoffs that significantly degrade other aspects of performance. This is particularly problematic in fractional-N PLLs wherein the input to the modulator usually is a constant and the output sequence from the modulator is converted to analog form and subjected to various nonlinear operations because of nonideal circuit behavior. The common approach to address spurious tones is to make the analog circuitry very linear so that the spurious tones have sufficiently low power for the given application. This limits design options and results in higher analog circuit power consumption than would be required if fewer linear analog circuits could be tolerated.
The tradeoffs tend to increase power consumption and circuit area, limit the choice of reference frequencies, and dictate low PLL bandwidths which preclude on-chip loop filters. They also become less effective in system-on-chip designs as CMOS circuit technology is scaled into the sub-100 nanometer regime. Therefore, the spurious tone problem negatively affects power consumption, cost, and manufacturability of wireless transceivers, and the problem gets worse as CMOS circuit technology scales with Moore's Law.
To address the quantization noise, researchers have described methods of implementing noise-shaped quantizers. See, e.g., A. J. Magrath and M. B. Sandler, “Efficient Dithering of Sigma-delta Modulators with Adaptive bit Flipping,” Electron. Lett, vol. 31, no. 11, pp. 846-847, May 1995; S. H. Yu, “Noise-Shaping Coding through Bounding the Frequency Weighted Reconstruction Error,” IEEE Trans. Circuits Syst. II: Expr. Briefs, vol. 53, no. 1, pp. 67-71, January 2006; D. E. Quevedo and G. C. Goodwin, “Multistep Optimal Analog-to-Digital Conversion,” IEEE Trans. Circuits and Systems I: Regular Papers, vol. 52,no. 3, pp. 503-515, March 2005; I. Daubechies and R. DeVore, “Approximating a Bandlimited Function Using Very Coarsely Quantized Data: A Family of Stable Sigma Delta Modulators of Arbitrary Order,” Ann. Math., vol. 158, no. 2, pp. 679-710, 2003.
Generally, known phase noise cancelling fractional-N PLLs are effective to cancel phase noises that result from mismatches between positive and negative current sources in the charge pump. However, these methods specifically focus on stabilizing noise-shaped coders and do not address the effect of nonlinearities on the quantization error.